Back in September 2012, JEDEC released the new DDR4 specification. With every new generation of DRAM the modules get faster and denser (we’ve gone from DDR1 DRAM with a top data-transfer rate of 200MT/s to DDR3 with widely available devices doing 2.1 GT/s) but there is more to this story than just numbers. The end goal of DDR4 DRAM is to see transfer rates of 3.2 GT/s; double what was originally specified for DDR3 (and that’s before the overclockers get their hands on it). But how exactly are they going to manage this?
When data is read from a RAM module, it is presented to the memory controller via the memory bus. The inherent problem with this is that the memory controller has to look at the bus at the right moment in order to accurately read the data. To allow the controller to read the data, RAM is specified with a hold time (tH).
Obviously, for faster timings this time needs to be reduced. With perfectly stable clocks, TH can theoretically be as short as the time the memory controller requires to latch the data. However, in real life nothing is perfect. As a general rule, one can assume a 50ps jitter for these clocks. In DDR1 at 200MT/s this window was 1200ps and so the 50ps jitter would only account for 4% of this data valid window.
Fast forward to the 1600 MT/s speeds of an average DDR3 module and suddenly this jitter takes up a one third of our data valid window (with other timings the real figure is closer to 40%). This in turn leads to more elaborate (read expensive) memory controllers and lots of wasted time on the bus. As can be seen, similar scaling would mean that at 3.2GT/s the TH would be almost entirely taken up by jitter.
The approach taken in DDR4 is to change the entire topology of the memory interlink. In a move analogous to the migration from PCI to PCIe the multi-drop bus has been abandoned in favour of a point-to-point topology. What this means to you is no more different colour slots to determine channels but rather that you will have one module per a channel. At the same time, the reduced controller complexity will mean that more channels are feasible so you’ll still be able to cram your rig full of memory modules.
The density of RAM modules is limited by today’s manufacturing technologies. Along with this, the DDR module size is already fixed so, as it stands, DDR modules have an upper cap on size. To counter this there is a reference in the module pinout for chip ID which describes a Through Silicon Via arrangement up to 8 slices high. TSV is a technology allowing for 3D Stacking of wafers within a die. Essentially this makes allowance for expansion of the modules along the axis orthogonal to the PCB. Another possible interpretation of this is that the ICs themselves could have allowances for stacking although this seems unlikely.
This doesn’t necessarily mean you’ll start seeing 64Gb modules appearing in the mainstream markets. Instead, predictions based on demand and cost would indicate that the modules will be widely available in the range from 2Gb to 16Gb with rarer 32Gb modules available at a premium. The spec itself only caters for 2, 4 and 8Gb modules with provisions made for the future introduction of a 16Gb module.
Continuing the trend, the power consumption is further reduced from the previous generation with DDR4 now running at 1.20V (+/- 0.06V) and containing unique commands to further improve the idle consumption (see section 4.29 Maximum Power Saving Mode). It seems likely that this operating voltage will be further reduced to 1.05V at a later date, just as DDR3 was reduced from 1.65V to 1.50V
One significant change on the power side is the requirement of an external VPP supply at 2.5V. VPP (the activating voltage) is normally generated by a capacitive charge pump on the die, taking up valuable real-estate within the silicon. Removing this allows for the inclusion of other components such as CRC calculators and parity checkers geared towards improved robustness.
In conclusion, you’ll be getting DDR4 along with your 14nm Skylake/Skymont processor from Intel sometime in 2015 (possibly earlier in a Broadwell Extreme processor and a little later from AMD if they don’t surprise us). Around this time, DDR4 production will start ramping up towards 50% market penetration and costs will have come down to DDR3 ranges per a module (somewhere around ¼ the current price per a Gb). When you put together your new machine, you may notice that the new RAM modules are ever so slightly chunkier than the old and now have 284 pins as opposed to the 240 pins on DDR3. The slots will all be the same colour and you won’t have to feel funny putting in an odd number of modules; the new architecture should mean that your matched kits are no longer necessary.
The new, reliability features will mean far fewer random lockups and smoother operation while the power features will have a huge impact on your mobile devices. Unlike with the progression from DDR2 to DDR3 you will not see dual memory type motherboards. The changes in the bus topology make this unfeasible to say the least.
Speculation for the enthusiasts
As for overclocking, things could go either way. The inclusion of the reliability features on the die could add heat but, on the whole, this should be balanced by the removal of VPP regulation. The lower power consumption will improve thermal characteristics but the reduced timing will increase the likelihood of errors. These errors, in turn, will be more likely to cause lockups than blue screens though, due to the reliability features. Essentially, there’s less room for latching errors but an increased chance of recovery and a good chance (although not guaranteed) of improved thermal characteristics.
TSV ICs will be problematic for cooling. The stacked wafers will reduce the ability of the lower wafers to dissipate heat. This means that results will be far superior with smaller modules than with larger ones. For more information, please see the DDR4 specification. Philip Barlow